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The DB_EPCQ IP-Core provides random access to EPCQ devices. The IP-Core is delivered as a QSys component and maps the entire flash memory into the address map of a QSys design. The memory can easily be accessed by normal pointer operation - without complex access functions. NIOS applications can locate the reset vector directly into the Flash address span and on startup the NIOS application doesn't require any bootloader in on-chip Memory.

For erase operation a second interface is provided that allows sector and subsector erase commands or erase of the entire flash device.

The DB_EPCQ IP-Core uses the ASx4 Pins of Cyclone V devices and ASx1 Pins of the Cyclone III / IV devices. Alternatively the IP-Core supports normal FPGA IO Pins to connect an additional QSPI Flash for data / program storage. the DB_EPCQ IP-Core is compatible with the Active Serial configuration and the Remote Update controller of the FPGA.




  • Supported FPGA families:
    • Cyclone III
    • Cyclone IV
    • Cyclone V
    • Cyclone 10
  • Supported Quartus Versions
    • Quartus 13.1
    • Quartus 14.1
    • Quartus 15.1
    • Quartus 16.1
    • Quartus 17.1
  • Supported QSPI devices
    • Altera EPCQ16 .. EPCQ512
    • Micron N25Q16 .. N25Q00
    • Altera EPCQ16A .. EPCQ128A
    • Winbond W25Q16 .. W25Q256
  • Open-Core-Plus test version is available in the download section




  • 1499.00€ (incl. VAT: 1783.81€)